Direct Memory Access
DMA is an necessary characteristics of all modern computers, as it permits devices to transfer data without subjecting the CPU to a heavy in the clouds. or else, the CPU would have to copy each piece of data from the source to the destination, making it unavailable for other tasks. This situation is motivated because access to I/O devices over a peripheral bus is normally slower than regular system RAM. With DMA, the CPU obtains freed from this above your head and can do useful tasks during data transfer (though the CPU bus would be partly blocked by DMA). In the same way, a DMA engine in an embedded processor allows its dispensation element to issue a data transfer and carries on its own task while the data transfer is being performed.
A DMA transfer copies a block of memory from one device to another. While the CPU starts the transfer by issuing a DMA command, it does not execute it. For so-called "third party" DMA, as is usually used with the ISA bus, the transfer is executed by a DMA controller which is normally part of the motherboard chipset. More sophisticated bus designs such as PCI usually use bus mastering DMA, where the device takes control of the bus and makes the transfer itself. In an embedded processor or multiprocessor system-on-chip, it is a DMA engine linked to the on-chip bus that essentially administers the transfer of the data, in coordination with the flow control mechanisms of the on-chip bus.
A DMA transfer copies a block of memory from one device to another. While the CPU starts the transfer by issuing a DMA command, it does not execute it. For so-called "third party" DMA, as is usually used with the ISA bus, the transfer is executed by a DMA controller which is normally part of the motherboard chipset. More sophisticated bus designs such as PCI usually use bus mastering DMA, where the device takes control of the bus and makes the transfer itself. In an embedded processor or multiprocessor system-on-chip, it is a DMA engine linked to the on-chip bus that essentially administers the transfer of the data, in coordination with the flow control mechanisms of the on-chip bus.
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